1st lesson free
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PRANAV
- Rate UGX 50,437
- Response 1h
UGX 50,437/hr
Contact
1st lesson free
- Engineering
- Electronics
I am currently working as PhD scholar and previously worked as Industrial Trainer in VLSI. I can teach Verilog HDL, FPGA Architecture, Digital Electronics, etc.
- Engineering
- Electronics
Lesson location
About PRANAV
I am a VLSI Design Engineer and published researcher with an M.Tech in VLSI Design from Amrita Vishwa Vidyapeetham, Bengaluru (2026). My research paper has been accepted at the IEEE DISCOVER 2026 international conference — demonstrating that I stay current with the latest developments in semiconductor and hardware design.
I have over 8 months of active teaching experience — training graduate engineering students at multiple institutes in Verilog HDL, SystemVerilog, UVM verification, FPGA implementation, and digital design flows. I currently work as a PhD scholar and Teaching Assistant for an FPGA laboratory at university level, where I design and deliver hands-on lab sessions weekly.
My industry tool experience includes Cadence Genus, Cadence Innovus, Cadence Tempus, and Xilinx Vivado — the same tools used by companies like Intel, Qualcomm, and NXP. This means my students learn not just theory but real industry-standard workflows.
I am patient, structured, and genuinely passionate about making complex concepts simple and approachable. My students consistently tell me that what confused them for months became clear in one session.
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About the lesson
- Primary
- Secondary
- Tertiary
- +7
levels :
Primary
Secondary
Tertiary
University
Adult Education
Masters
Diploma
PhD (Doctor of Philosophy)
MBA
Early childhood education
- English
All languages in which the lesson is available :
English
I am a VLSI Design engineer with an M.Tech from Amrita Vishwa Vidyapeetham (June 2026, CGPA 8.3) and hands-on experience in RTL design, digital electronics, FPGA implementation, and hardware verification. I have been actively teaching VLSI concepts to postgraduate students for over a year across multiple institutes and currently work as a Teaching Assistant for FPGA lab at a university.
My teaching approach:
I believe in learning by doing. Every concept I teach is immediately followed by a practical example — either on paper, EDA Playground, or Xilinx Vivado. I never let a student leave a session without writing at least one line of working code.
Typical class structure:
I start with a concept explanation in simple language, connect it to a real-world application, then move to hands-on coding or simulation. I end every session with a small quiz or problem to confirm understanding.
What makes me different:
I have an accepted research paper at IEEE DISCOVER 2026 and hands-on experience with industry tools like Cadence Genus, Innovus, and Tempus — so I teach not just theory but real industry practice.
Who can learn from me:
B.Tech and M.Tech students in Electronics, Electrical, and Computer Engineering studying Digital Design, VLSI, RTL, FPGA, SystemVerilog, UVM, or preparing for semiconductor industry interviews.
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Rates
Rate
- UGX 50,437
Pack prices
- 5h: UGX 250
- 10h: UGX 500
free lessons
The first free lesson with PRANAV will allow you to get to know each other and clearly specify your needs for your next lessons.
- 1hr
online
- UGX 50,437/hr
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